1. Field of the Invention
The present invention relates to a semiconductor memory embedded in a single chip microcomputer, and particularly to a semiconductor memory and its test method including a test circuit for testing an inter-bit-line interference suppression function.
2. Description of Related Art
A semiconductor memory such as a mask ROM usually precharges its bit lines to place them at a middle potential before reading to accelerate its processing speed. Such a semiconductor memory, however, has a problem in that when it is mounted on a high-speed microcomputer, it often undergoes electrical interference from bit lines adjacent to a memory transistor from which the data is to be read, making it difficult to maintain its precharge potential, and to read correct data.
FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory (mask ROM) that presents the foregoing problem involved in reading. In this figure, the reference numeral 10 designates bit lines for selecting a memory transistor. In the example of FIG. 5, bit lines B1, . . . , Bnxe2x88x921, Bn, Bn+1, . . . , BN are connected to a bit-line selector 20, where suffixes 1-N are positive integers. The reference numeral 20 designates the bit-line selector that decodes the address to selectively connect one of the bit lines 10 corresponding to the address with one of sense amplifiers 30. The reference numeral 30 designates the sense amplifiers for detecting and amplifying signals read from the memory transistors; and 40 designates word lines for selecting the memory transistors. In the example of FIG. 5, word lines W1, W2 and W3 are connected to a word-line selector 50 for decoding an address and for asserting one of the word lines 40 corresponding to the address; and each reference numeral 60 designates a wiring capacitance, a parasitic capacitance between adjacent bit lines 10 and 10. Finally, reference symbols T1xe2x88x921-T1xe2x88x92N, T2xe2x88x921-T2xe2x88x92N and T3xe2x88x921-T3xe2x88x92N designate memory transistors placed at individual intersections of the bit lines 10 and the word lines 40.
Next, the operation of the conventional semiconductor memory will be described.
FIG. 6 is a timing chart illustrating the read operation of the semiconductor memory of FIG. 5. Referring to FIG. 6, the problem involved in reading of the semiconductor memory will be described.
First, let us assume that according to an address signal input to the semiconductor memory, the data is read from the memory transistor T1xe2x88x92(n+1) at the intersection point of the bit line Bn+1 and the word line W1. In this case, the bit-line selector 20 selects the bit line Bn+1, and precharges its potential beyond the threshold value of the sense amplifiers 30. After completing the precharge, the potential of the bit line Bn+1 is supplied to the corresponding sense amplifier 30. If the potential is higher than the threshold value of the sense amplifier 30, a H (high) level value is read, and otherwise a L (low) level value is read. In this example, the memory transistor T1xe2x88x92(n+1) at the intersection point of the word line W1 and the bit line Bn+1 has its drain disconnected with the bit line, or its gate is always kept off according to the data content of the ROM. Accordingly, even if the word-line selector 50 asserts the word line W1, the potential of the bit line Bn+1 is maintained at the H level as illustrated in FIG. 6. In contrast, as for the memory transistor T1xe2x88x92n with its drain connected to the bit line, when the word-line selector 50 asserts the word line W1, its gate is turned on and the bit line is grounded, thereby outputting the L level.
Next, assume that according to the address signal input to the semiconductor memory, the data is read from the memory transistor T2xe2x88x92(nxe2x88x921) at the intersection point of the bit line Bnxe2x88x921 and the word line W2. In this case, the potential of the bit line Bnxe2x88x921 is also maintained at the H level in the same manner as with the memory transistor T1xe2x88x92(n+1).
Finally, assume that according to the address signal input to the semiconductor memory, the data is read from the memory transistor T3xe2x88x92n at the intersection point of the bit line Bn and the word line W3. Since the memory transistor T3xe2x88x92n is set at the H level, the potential of the bit line Bnmust be maintained at the H level, as well. In this case, however, the following problem arises.
The memory transistors T3xe2x88x92(n1xe2x88x92) and T3xe2x88x92(n+1) which are adjacent to the memory transistor T3xe2x88x92n, and placed at the intersection point of the bit line Bnxe2x88x921 and word line W3 and that of the bit line Bn+1 and word line W3, respectively, are set at the ON state as illustrated in FIG. 6. In other words, the two adjacent memory transistors T3xe2x88x92(nxe2x88x921) and T3xe2x88x92(n+1) have their drains connected to the bit lines Bnxe2x88x921 and Bn+1, or have their gates brought into the ON state when the word line W3 is asserted. In addition, the word line connected to their gates is also connected to the gate of the memory transistor T3xe2x88x92n which is to be read presently.
Therefore, when the word line W3 is asserted, that is, when a H level signal is supplied to the word line W3 to select the memory transistor T3xe2x88x92n, the gates of the two adjacent memory transistors T1xe2x88x92(n+1) and T2xe2x88x92(nxe2x88x921) are brought into the ON state, so that the H level potentials held on the bit lines Bnxe2x88x921 and Bn+1 at the reading fall toward the ground potential.
Here, there are wiring capacitances or parasitic capacitances between the bit line Bn and its adjacent bit lines Bnxe2x88x921 and Bn+1. Therefore, the potential of the bit line Bn which must keep its potential at the H level drops slightly because of the interference from the adjacent bit lines Bnxe2x88x921 and Bn+1 whose potentials fall to the ground potential. If the potential of the bit line Bn drops below the threshold value of the sense amplifiers 30 as illustrated in FIG. 6, the L level value is erroneously read instead of the correct H level value. Thus, the conventional semiconductor memory has a problem in that it likely to read the ROM data erroneously because of the interference from the adjacent bit lines.
To solve the problem due to the inter-bit-line interference, a method is know that connects resistors called a leaker to the bit lines.
FIG. 7 is a circuit diagram showing a configuration of a mask ROM as a conventional semiconductor memory with a leaker. In this figure, the reference numeral 70 designates resistors connected between the bit lines 10 and the ground potential as the leaker; 80 designates a power supply (Vcc) for precharging bit lines 10; and 90 designates a load resistor connected between the power supply 80 and the bit-line selector 20 to prevent the potential of the bit lines 10 from falling during reading the H level. Although the resistors 70 are used as the leaker in this example, ON transistors can be used instead. In addition, the driving power of the leaker is set less than that of the precharge circuit. In FIG. 7, the same reference numerals designate the same or like components to those of FIG. 5, and the description thereof is omitted here.
Next, the operation of the conventional semiconductor memory will be described.
FIG. 8 is a timing chart illustrating the read operation of the semiconductor memory of FIG. 7. The function of the leaker will be described with reference to FIG. 7.
First, just as in FIG. 5, according to the address signal input to the semiconductor memory, the data is read from the memory transistor T1xe2x88x92(n+1) placed at the intersection point of the bit line Bn+1 and the word line W1, and then from the memory transistor T2xe2x88x92(nxe2x88x921) placed at the intersection point of the bit line Bnxe2x88x921 and the word line W2.
Since the memory transistors T1xe2x88x92(n+1) and T2xe2x88x92(nxe2x88x921) store the H level value, the bit lines Bnxe2x88x921 and Bn+1 will maintain the H level potential at the precharge without the leaker.
Actually, however, in the semiconductor memory of FIG. 7, the potentials of the bit lines Bnxe2x88x921 and Bn+1 gradually drop from the H level to the ground level before the data stored in the memory transistor T3xe2x88x92n is read, because of the resistors 70 connected to the bit lines Bnxe2x88x921 and Bn+1 as the leaker.
When the word line W3 is asserted to select the memory transistor T3xe2x88x92n thereafter, both the potentials of the bit lines Bnxe2x88x921 and Bn+1 have dropped to intermediate potentials between the H level and the ground level. Accordingly, as illustrated in FIG. 8, the interference from the adjacent bit lines is alleviated, preventing the potential of the bit line Bn from falling below the threshold value of the sense amplifiers 30. As a result, the correct H level output value is obtained from the memory transistor T3xe2x88x92n.
As another measure taken against the problem of the interference between the bit lines, a discharger can be connected to the bit lines.
FIG. 9 is a circuit diagram showing a configuration of a conventional mask ROM as a semiconductor memory with such a discharger. In this figure, the reference numeral 100 designates N-channel transistors connected between the bit lines 10 and the ground potential as the discharger; and 110 designates a discharge signal supplied to the gates of the N-channel transistors 100 as the discharger for asserting or deasserting them. In FIG. 9, the same reference numerals designate the same or like components to those of FIG. 5, and the description thereof is omitted here.
Next, the operation of the conventional semiconductor memory will be described.
FIG. 10 is a timing chart illustrating the read operation of the semiconductor memory of FIG. 9. The function of the discharger will be described with reference to FIG. 9.
First, just as in FIG. 5, according to the address signal input to the semiconductor memory, the data is read from the memory transistor T1xe2x88x92(n+1) placed at the intersection point of the bit line Bn+1 and the word line W1, and then from the memory transistor T2xe2x88x92(nxe2x88x921) placed at the intersection point of the bit line Bnxe2x88x921 and the word line W2.
Since the memory transistors T1xe2x88x92(n+1) and T2xe2x88x92(nxe2x88x921) store the H level value, the bit lines Bnxe2x88x921 and Bn+1 will maintain the H level potential at the precharge without the discharger.
Actually, however, in the semiconductor memory of FIG. 9, the potentials of the bit lines Bnxe2x88x92l and Bn+1 are dropped from the H level to the ground level before the data stored in the memory transistor T3xe2x88x92n is read, because of the H level discharge signal 110 supplied to the N-channel transistors 100.
When the word line W3 is asserted to select the memory transistor T3xe2x88x92n thereafter, both the potentials of the bit lines Bnxe2x88x921 and Bn+1 have already dropped to the ground level. Accordingly, as illustrated in FIG. 10, the interference between the adjacent bit lines is alleviated, thereby preventing the potential of the bit line Bn from falling below the threshold value of the sense amplifiers 30. As a result, a correct H level output value is obtained from the memory transistor T3xe2x88x92n.
Thus, the conventional semiconductor memories install the circuits for alleviating the interference between the bit lines to prevent the erroneous read from taking place.
As for the semiconductor memories, a test is implemented to check whether it can write or read data correctly. The test of the semiconductor memory is usually carried out for each address, that is, for each memory transistor using a test pattern in accordance with the data stored in the individual memory transistors.
With the foregoing configurations, the conventional semiconductor memories have a problem in that it is very difficult for them to test the function of the circuits installed for suppressing the interference between the adjacent bit lines.
The problem will be described more specifically. To test the function of the circuit installed to suppress the interference between the adjacent bit lines, it is necessary to design the test pattern by analyzing the freely stored data in the semiconductor memory to search for such an address sequence of the memory transistors as bringing about the inter-bit-line interference. Thus, the pattern for generating the inter-bit-line interference differs for each semiconductor memory.
Therefore, to test the function of the circuit installed for suppressing the interference between the adjacent bit lines, test patterns for the inter-bit-line interference must be designed for each semiconductor memory before testing the product, which is a very time-consuming work.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor memory and its test method capable of facilitating estimation and test on the function of the circuit for suppressing the interference between the bit lines independently of the stored data by installing an inter-bit-line interference test circuit.
According to a first aspect of the present invention, there is provided a semiconductor memory comprising: a memory cell block including a plurality of memory cells placed at individual intersection points of a plurality of word lines and a plurality of bit lines that are arranged in a matrix fashion; an inter-bit-line interference suppression circuit connected to the plurality of bit lines, for releasing potentials of bit lines adjacent to a memory cell whose data is to be read among the memory cells of the memory cell block, thereby suppressing electrical interference between the bit lines; means for precharging, before reading data stored in a memory cell to be tested, at least bit lines adjacent to a bit line corresponding to the memory cell to be tested among the plurality of bit lines;
test memory cell selector for asserting a word line of the memory cell to be tested that is connected to a bit line between the bit lines precharged by the means for precharging; and a decision circuit for deciding as to whether the inter-bit-line interference suppression circuit operates normally or not in response to the data stored in the memory cell to be tested or to potential changes of the bit lines precharged.
Here, the semiconductor memory may further comprise a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, wherein the means for precharging may consist of a bit line selector, and the test memory cell selector may produce the potential changes of the precharged bit lines by asserting one of the word lines of the test memory cell block, and select a memory cell that is connected to a bit line between the bit lines with their potentials changed from the test memory cell block as the memory cell to be tested.
The means for precharging may consist of a precharge circuit for precharging all the bit lines simultaneously, and the test memory cell selector may select a memory cell that is connected to a bit line between the bit lines precharged by the precharge circuit from the memory cell block as the memory cell to be tested.
The semiconductor memory may further comprise a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, wherein the means for precharging may consist of a precharge circuit for precharging all the bit lines simultaneously, and the test memory cell selector may produce the potential changes of the precharged bit lines by asserting one of the word lines of the test memory cell block, and select a memory cell that is connected to a bit line between the bit lines with their potentials changed from the test memory cell block as the memory cell to be tested.
At least one of a gate width and a gate length of the memory cells of the test memory cell block may be greater than those of the memory cells constituting the memory cell block.
The test memory cell selector may assert the word line of the test memory cell block by a potential higher than a potential used in an actual operation.
The means for precharging may precharge the bit lines up to a potential higher than a potential used in an actual operation.
The test memory cell selector may assert the word line of the memory cell block by a potential higher than a potential used in an actual operation.
The semiconductor memory may further comprise source potential modifying means for bringing a source potential of the transistors constituting the memory cells to a potential equal to or less than a ground level.
According to a second aspect of the present invention, there is provided a test method of a semiconductor memory including a memory cell block having a plurality of memory cells placed at individual intersection points of a plurality of word lines and a plurality of bit lines that are arranged in a matrix fashion, and an inter-bit-line interference suppression circuit connected to the plurality of bit lines, for releasing potentials of bit lines adjacent to a memory cell whose data is to be read among the memory cells of the memory cell block, thereby suppressing electrical interference between the bit lines, the test method of a semiconductor memory comprising the steps of: precharging at least bit lines adjacent to a bit line corresponding to a memory cell to be tested among the plurality of bit lines; asserting a word line of the memory cell to be tested that is connected to a bit line between the bit lines precharged; and deciding, in response to the data stored in the memory cell to be tested or to potential changes of the bit lines precharged, as to whether a suppression function of the inter-bit-line interference suppression circuit operates normally or not against electrical interference from the bit lines adjacent to the memory cell to be tested.
Here, the semiconductor memory may further comprise a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, wherein the step of asserting may produce the potential changes of the precharged bit lines by asserting one of the word lines of the test memory cell block, and select a memory cell connected to a bit line between the bit lines with their potentials changed from the test memory cell block as the memory cell to be tested.
The step of precharging may precharge all the bit lines simultaneously, and the step of asserting may select a memory cell that is connected to a bit line between the precharged bit lines from the memory cell block as the memory cell to be tested.
The semiconductor memory may further comprise a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, wherein the step of precharging may precharge all the bit lines simultaneously, and the step of asserting may produce the potential changes of the precharged bit lines by asserting one of the word lines of the test memory cell block, and select a memory cell connected to a bit line between the bit lines with their potentials changed from the test memory cell block as the memory cell to be tested.